1. Field of the Invention
The invention relates in general to a memory channel access to a memory and, in particular, to memory channel traffic control when multiple memory channels are accessing the memory.
2. Description of the Prior Art
In a conventional arbiter design, only bandwidth requirements are taken into consideration when deciding arbitration weighting. However, address locality and contiguous factor are important factors to consider in order to reduce the overheads of pre-charge and processing time of active commands while a channel is accessing a memory module containing DRAM, or alike, devices.
Conventionally, as shown in FIG. 1, in a system-on-chip (SOC) 100, an arbiter 105 is used to arbitrate the traffic from CPU 102, DMA engine A 103 and DMA engine B 104 to a system memory such as DDR SDRAM module 101 through a DDR controller core and physical interface 106. A weighted-fair arbitration algorithm is often used by the arbiter 105 to share the system memory bandwidth among all the ports according to the weighted settings assigned for each port. However, the performance of memory accessing based on the weighted-fair arbitration algorithm will be degraded due to the fact that it needs to handle re-scheduling and out of order issues in order to optimize memory page hit rate when the memory is accessed by multiple channels concurrently.
Therefore, what is needed is a new arbitration scheme to obtain optimal page hit rate of the memory channel and to resolve the re-scheduling and out of order issues.